During post-silicon validation, manufactured integrated circuits areextensively tested in actual system environments to detect design bugs. Buglocalization involves identification of a bug trace (a sequence of inputs thatactivates and detects the bug) and a hardware design block where the bug islocated. Existing bug localization practices during post-silicon validation aremostly manual and ad hoc, and, hence, extremely expensive and time consuming.This is particularly true for subtle electrical bugs caused by unexpectedinteractions between a design and its electrical state. We present E-QED, a newapproach that automatically localizes electrical bugs during post-siliconvalidation. Our results on the OpenSPARC T2, an open-source500-million-transistor multicore chip design, demonstrate the effectiveness andpracticality of E-QED: starting with a failed post-silicon test, in a few hours(9 hours on average) we can automatically narrow the location of the bug to(the fan-in logic cone of) a handful of candidate flip-flops (18 flip-flops onaverage for a design with ~ 1 Million flip-flops) and also obtain thecorresponding bug trace. The area impact of E-QED is ~2.5%. In contrast,deter-mining this same information might take weeks (or even months) of mostlymanual work using traditional approaches.
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